In recent years, higher density and higher reliability are strongly demanded for mounting technology as electronic equipments have been rapidly marching to the goal of the light/slim/short/small trend. Under such circumstances, with getting smaller and slimmer size of mounted components, in the reflow process in which components are mounted on printed circuit boards with solder, warps of printed circuit boards and mounted components get larger by heat and it is pointed out that the connecting reliability might get worse when components are mounted on the printed circuit boards under such conditions. Therefore it is highly necessary in order to solve these problems to estimate the warp movements under the reflow process quantitatively and accurately before the actual ones.
However, as it is very difficult to monitor generating warps under high temperature, the estimation technique by a simulation using the Finite Element Method (FEM) is studied at associated enterprises, universities and research institutes at present. For example, the warp analysis system for printed circuit boards, being multilayered board, is proposed in the patent document 1. And estimating methods by applying theoretical formula can be considered in addition to the FEM, and there is the multilayered beam theory in the non-patent document 1 in order to handle the warps of multilayered boards, moreover there is the patent document 2 in order to handle the warps in conditions that components are mounted on the multilayered boards.    Patent document 1: Japanese patent Laid-open publication No. 2004-013437    Patent document 2: Japanese patent Laid-open publication No. 2006-278803    Non-patent document 1: written by Oda, Juhachi “The evaluation of stress and deformation of printed circuit boards by the multilayered beam theory”, Transactions of The Japan Society of Mechanical Engineers; Vol. 59 No. 563 (1993), pp. 203-208